The present inventive concept relates to bus systems, interconnects, and operating methods for systems including a System On Chip (SOC).
SOCs are well known devices in which multiple integrated circuit chips (or chip blocks), potentially performing different functions, are commonly integrated onto a single substrate (“chip”) or within a single semiconductor package. In order to satisfy the demands of a rapidly changing market, it is necessary to reduce the time required to design, develop and/or fabricate a SOC. One technique used to improve a new SOC's time to market essentially recycles existing chip blocks or chip IP cores. The recycling of an IP core is effective not only in reducing development time, but also improving the reliability of the new SOC.
On the other hand, efficient operation of a SOC requires a bus system that effectively interconnects the multiple chip blocks within the SOC. Unfortunately, the bus systems used in conventional SOCs are not readily adapted to the architectural changes inherent in a re-design of chip blocks, regardless of IP core recycling.